Programme of DCC at ETAPS 2010

(Designing Correct Circuits)

Saturday, March 20

09:00 - 10:30 SESSION 1: Formal Approaches

09.00: Formal Validation and Verification of Networks-on-Chips: Status
and Perspective

Julien Schmaltz, Freek Verbeek, Tom van den Broek (OpenUniversity of The Netherlands)

09.45: A Formalised Framework for Incremental Modelling of On-Chip Communication

Peter Boehm (University of Oxford)

10:30 - 11:00 Coffee

11:00 - 12:30 SESSION 2: Formal Approaches

11.00: Gap-Free verification of weakly programmable IPs against their
operational ISA model

Markus Wedler, Sacha Loitz, Wolfgang Kunz (University of
Kaiserslautern)

11.45: A Prototype Embedding of Bluespec SystemVerilog in the SAL Model Checker

Dominic Richards, David Lester (University of Manchester)

12:30 - 14:00 Lunch

14:00 - 15:30 SESSION 3: Bluespec Systemverilog

14.30: Introducing Kind #: The Numeric Type System of Bluespec SystemVerilog

Ravi Nanavati

15.00: Modular Refinement of Bluespec Hardware Designs

Nirav Dave (Massachusetts Institute of Technology), Michael
Katelman (University of Illinois at Urbana-Champaign)