Programme of DCC at ETAPS 2010

(Designing Correct Circuits)

Sunday, March 21

09:00 - 10:30 SESSION 4: Languages

09.00: A Proposal for a More Generic, More Accountable, Verilog

Cherif Salama, Walid Taha (Rice University)

09.45: A High-Level Language for Testing

Michael Katelman and Jose Meseguer (University of Illinois at
Urbana-Champaign)

10:30 - 11:00 Coffee

11:00 - 12:30 SESSION 5: Languages

11.00: Clock typing of n-Synchronous Programs

Louis Mandel, Florence Plateau, Marc Pouzet (Universite
Paris-Sud and INRIA)

11.45: Discussion

12:30 - 14:00 Lunch

14:00 - 15:30 SESSION 6: Design and Synthesis

14.00: Synthesis of Data Parallel GPU Software into FPGA Hardware

Satnam Singh (Microsoft Coroporation)

14.45: Chalk, a language and tool for architecture design and analysis

Wouter Swierstra, Koen Claessen, Carl Seger, Mary Sheeran, Emily
Shriver (Chalmers UniversitY of Technology and Intel
Coroporation)