Programme of DCC at ETAPS 2006
Saturday, March 25
09:30 - 10:30 SESSION 1 (DCC, Saturday, March 25, room: EI 2)
- Model Checking / Abstraction
- Microprocessor Verification Based on Datapath Abstraction and Refinement
- Zaher S. Andraus, Mark H. Liffiton, and Karem A. Sakallah (Univ. of Michigan, USA)
- Reachability Analysis with QBF
- Armin Biere (Johannes Kepler Univ., A)
10:30 - 11:00 Coffee
11:00 - 12:30 SESSION 2 (DCC, Saturday, March 25, room: EI 2)
- Clocking
- An Implementation of Clock-Gating and Multi-Clocking in Esterel
- Laurent Arditi, Gérard Berry, Marc Perreaut (Esterel Technologies), and Mike Kishinevsky (Intel)
Easy
Parameterized Verification of Cross Clock-Domain Protocols
- Geoffrey Brown (Indiana Univ., IND) and Lee Pike (Galois Connections)
- Towards the Correct Design of Multiple Clock Domain Circuits
- Joe Stoy (Bluespec Inc.)
12:30 - 14:00 Lunch
14:00 - 15:30 SESSION 3 (DCC, Saturday, March 25, room: EI 2)
- Verification Methodology
- Evolution and Impact of a Large Industrial Proof
- Robert B. Jones and Noppanunt Utamaphethai (Intel)
- Is Feature-Oriented Verification Useful for Hardware?
- Kathi Fisler (Worcester Polytechnic, USA) and Shriram Krishnamurthi (Brown Univ., USA)
- A Coverage Analysis for Safety Property Lists
- Koen Claessen (Chalmers, SE)
15:30 - 16:00 Coffee
16:00 - 17:00 SESSION 4 (DCC, Saturday, March 25, room: EI 2)
- Synthesis
- Towards Automatically Compiling Efficient FPGA Hardware
- Jean Baptiste Note and Jean Vuillemin (Ecole Normale Supérieure, F)
- Proof Producing Synthesis of Arithmetic and Cryptographic Hardware
- Konrad Slind, Scott Owens (Univ. of Utah, USA), Juliano Iyoda, and Mike Gordon (Univ. of Cambridge, GB)
Sunday, March 26
09:30 - 10:30 SESSION 1 (DCC, Sunday, March 26, room: EI 2)
- Circuits / Design
- Networks of Elastic Circuits
- Sava Kristić, Mike Kishinevsky, and John O'Leary (Intel), and Jordi Cortadella (UPC, Barcelona, E)
- Self-Healing Reconfigurable Manifolds
- Sarah Thompson and Alan Mycroft (Univ. of Cambridge, UK)
10:30 - 11:00 Coffee
11:00 - 12:30 SESSION 2 (DCC, Sunday, March 26, room: EI 2)
- Functional Languages I
- Using Wired for Design Exploration
- Emil Axelsson, Koen Claessen, and Mary Sheeran (Chalmers, SE)
- Interconnect and Geometric Layout in Hydra
- John T. O'Donnell (Univ. of Glasgow, UK)
- A Functional HDL for ReFLect
- Tom Melham (Oxford Univ., UK) and John O'Leary (Intel)
12:30 - 14:00 Lunch
14:00 - 15:30 SESSION 3 (DCC, Sunday, March 26, room: EI 2)
- Functional Languages II
- Verification of Circuit Generators
- Warren A. Hunt, Jr. and Erik Reeber (Univ. of Texas at Austin, USA)
- Two-level Languages and Circuit Design and Synthesis
- Walid Taha (Rice Univ., USA)
- The Design of a Floating Point Execution Unit Using the Integrated Design and Verification (IDV) System
- Carl Seger (Intel)
15:30 - 16:00 Coffee
16:00 - 17:00 SESSION 4 (DCC, Sunday, March 26, room: EI 2)
- Easing Verification
- Automating the Verification of RTL-Level Pipelined Machines
- Panagiotis Manolios (Georgia Inst. of Technology, USA)
- Another Dimension to High Level Synthesis: Verification
- Malay K. Ganai, Aarti Gupta, Akira Mukaiyama, and Kazutoshi Wakabayashi (NEC)
19:30 SOCIAL EVENT (Sunday, March 26)
- Joint Workshops Pre-Conference Dinner
- Dinner at the historic restaurant Piaristenkeller, Piaristengasse 45, 1080 Wien
Further ETAPS 2006 Programme Information:
- Programme Overview
- Main Conferences:
Complete Programme,
CC,
ESOP,
FASE,
FOSSACS,
TACAS
- Workshops:
ACCAT,
AVIS,
CMCS,
COCV,
EAAI,
FESCA,
FRCSS,
GT-VMT,
LDTA,
MBT,
QAPL,
SC,
SLAP,
SPIN,
TERMGRAPH,
WITS,
WRLA
- Tutorials:
Phoenix,
QuantComp
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Last Update: 2006-03-23